1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices, and, more particularly, to packaging circuit chips by attaching a carrier substrate to a chip using an underfill material.
2. Description of the Related Art
As semiconductor manufacturers continue to scale down on-chip features, the need to contact those reduced size features becomes a more significant constraint. The number of scaled features provided for increased functionality, i.e., in general, the number of inputs and outputs (I/O count) of an integrated circuit, may be increased while maintaining the chip size or, on the other hand, the chip size may be reduced while maintaining the functionality (and the I/O count) of the integrated circuit. In both cases, however, the density of inputs and outputs (I/Os) is increased. For a conventional peripheral bond pad arrangement, the resulting bond pad pitch, i.e., the distance between the center of two adjacent bond pads, is accordingly reduced.
Semiconductor devices including integrated circuitry are typically formed on appropriate substrates or wafers, such as silicon wafers, silicon-on-insulator (SOI) wafers, glass wafers and the like, wherein usually a large number of individual semiconductor devices, such as CPUs, memory chips, ASICs (application specific ICs) and the like, are formed simultaneously on the wafer. Depending on the complexity of the semiconductor devices under consideration, up to 500 or more interrelated processes may be required to complete the semiconductor devices on wafer level. Due to economical constraints, feature sizes of individual circuit elements, such as transistors, are continuously being scaled, thereby increasing package density per unit area of the wafer, while, at the same time, wafers of increased surface area are employed to enhance production yield, since most of the highly complex manufacturing processes may be performed on wafer basis rather than die basis. Typically, as package densities of the individual circuit elements increase, the complexity of the individual semiconductor devices may also increase, thereby frequently requiring an increased number of input/output terminals for contacting the periphery.
Packaging of the individual semiconductor devices after dicing the wafer also plays an important role in view of cost efficiency of the overall manufacturing process, as well as with respect to device performance and reliability. A packaging technique has recently become a standard procedure, at least for highly complex semiconductor devices, in which each semiconductor device is provided with a specifically designed contact layer, also often referred to as a “bump layer.” The bump layer typically includes a plurality of contact pads, with adhesive bumps or solder bumps which may provide thermal or electrical contact to underlying circuit elements or which may be provided in view of mechanical stability of the semiconductor device in the package. The semiconductor device may then be directly attached to an appropriate carrier substrate or printed wiring board, which has a contact pad array that matches the layout of the bump layer of the semiconductor device, wherein the bonding of the carrier substrate and the semiconductor device may be accomplished by reflowing the bump material or adhesive, thereby substantially simultaneously contacting all of the solder bumps with the respective contact pads on the carrier substrate.
Thus, contrary to traditional wire bonding techniques, extremely short electrical connections between the semiconductor device and the carrier substrate are accomplished in a highly efficient manner, thereby providing low ohmic connections with low parasitic inductance, wherein additionally, the entire semiconductor surface is substantially available for providing contact areas, contrary to the traditional wire bonding techniques that are substantially restricted to the chip perimeter.
Despite the many advantages of this packaging technique compared to, for instance, conventional wire bonding techniques, problems may arise from the fact that the characteristics of the substrate material may significantly influence the overall performance of the packaged semiconductor device. In particular, the coefficient of thermal expansion (CTE), the conductor resistivity, the dielectric constant, the dielectric loss tangent and the thermal conductivity of the carrier substrate material may have to be taken into consideration when selecting appropriate carrier materials to appropriately balance material costs against device performance and reliability. For example, a mismatch in the coefficient of thermal expansion between the package or the printed wiring board and the die has a significant influence on product reliability. The mismatch in thermal expansion may generate shear stresses, which, in turn, may cause failure in the electrical connections.
FIG. 1 schematically shows a cross-sectional view of a semiconductor device 100 including a semiconductor chip 110 that is directly connected to a carrier substrate 120. The semiconductor chip 110 may comprise a plurality of contact pads 111 arranged in a corresponding pattern which matches a corresponding pattern of contact pads 121 formed on the carrier substrate 120. Corresponding contact pads 111 and 121 may be connected by a solder material 130 or a conductive adhesive material, thereby providing an electrical connection, also referred to as 130, between the semiconductor chip 110 and the carrier substrate 120. Moreover, in many semiconductor devices, including a semiconductor chip and a carrier substrate that are directly attached to each other, a fill material may be provided between the two components to enhance thermal and mechanical characteristics, as well as the integrity with respect to environmental influences.
In the example shown, a fill material, also referred to as underfill material 140, is provided between the semiconductor chip 110 and the carrier substrate 120. The underfill material 140 may comprise particles 141, which may substantially determine the thermal and mechanical characteristics of the underfill material 140, such as the thermal conductivity and the coefficient of thermal expansion. The underfill material 140 is provided in many applications to compensate for the differences in coefficients of thermal expansion between the semiconductor chip 110 and the carrier substrate 120. For example, the semiconductor chip 110 may be substantially comprised of a semiconductive material, such as silicon, and may have a coefficient of thermal expansion of approximately three parts per million per degree Celsius (ppm/C.), while the carrier substrate 120 may have a different coefficient, such as a difference of a few ppm/C. for an alumina ceramic substrate and may be as high as approximately 17-22 ppm/C. for an organic substrate comprised of FR4, which is frequently used due to its high cost efficiency and superior high frequency characteristics. Consequently, by coupling substantially the entire area of the semiconductor chip 110 to the substrate carrier 120, the effective thermal mechanical stress created during the operation of the semiconductor device 110 creates a “gradient” of the effective composite coefficient of thermal expansion between the semiconductor chip 110 and the carrier substrate 120, thereby increasing the reliability of the device 110, because the probability of a premature failure in one of the electrical connections 130 is significantly reduced.
A typical process flow for forming the device 110 may be carried out as follows. After the completion of the semiconductor chip 110 by forming circuit elements (not shown) and respective metallization layers (not shown), which are electrically connected to at least some of the contact pads 111, including solder bumps or solder balls, the corresponding chips 110 are diced to provide the individual semiconductor chip 110. Thereafter, the carrier substrate 120 and the semiconductor chip 110 are aligned to each other, contacted and heat treated to reflow the solder bumps or solder balls or any other bumps comprised of conductive adhesive to form the electric connections 130. Next, a precursor of the underfill material 140, for instance, in the form of a viscous epoxy containing the particles 141, which may be provided in the form of silica particles, is applied by dispensing a liquid precursor material along a single edge or along two adjacent edges of the gap between the semiconductor chip 110 and the carrier substrate 120. Surface tension then draws the liquid precursor material under the chip and through the array of electrical connections 130. Since the liquid flow is substantially governed by capillary flow, the entire process of distributing the liquid precursor material between the semiconductor chip 110 and the carrier substrate 120 may take several minutes, wherein the fluid flow is affected by the gap width, the pattern configuration of the electrical connections 130, the substrate temperature and gradients, the viscosity of the liquid precursor material, flux contamination, the dispense pattern used for applying the liquid precursor material, and the like. Thereafter, the device 110 may be heat-treated, for instance, in an oven, at temperatures from approximately 130-175° C. to cure the liquid precursor material and to form the underfill material 140. During the process of filling in the liquid precursor material, as well as during the heat treatment for curing the liquid, the particles 141 may move and accumulate at an interface 122 between the material 140 and the underlying carrier substrate 120. Since the particles 141 may significantly affect the thermal and mechanical characteristics of the underfill material 140, for instance, the coefficient of thermal expansion, undue thermomechanical stress may be created during the operation of the device 110, since the coefficient of thermal expansion of the underfill material 140 may be low at the interface 122 due to the accumulated particles 141, whereas the coefficient of thermal expansion of the underlying carrier substrate 120 may be significantly higher, thereby deteriorating the capability of thermal and mechanical stress “redistribution” of the underfill material 140.
In view of the situation described above, a need exists for an enhanced technique that enables the formation of packaged semiconductor devices having an underfill material, wherein one or more of the problems identified above, or at least the effects thereof, may be avoided or reduced.